The present invention relates to an improved semiconductor device including: a memory cell, in which the gate potential of a field effect transistor (FET) is controlled using a ferroelectric capacitor; and complementary MOS field effect transistors (CMOS).
An FET, called xe2x80x9cMFISFETxe2x80x9d, xe2x80x9cMFSFETxe2x80x9d or xe2x80x9cMFMISFETxe2x80x9d, has been known as a semiconductor memory device including a non-volatile storage section with a ferroelectric thin film in its gate. An FET with such a structure will be herein called a xe2x80x9cFeFETxe2x80x9d.
FIG. 6 is a cross-sectional view of a known FeFET implemented as an MFISFET. As shown in FIG. 6, the FET includes silicon substrate 101, silicon dioxide (SiO2) film 102, ferroelectric film 103, gate electrode 104 and source/drain regions 105 and 106. The SiO2 film 102, ferroelectric film 103 and gate electrode 104 are stacked in this order on the substrate 101. The ferroelectric film 103 is made of a metal oxide such as lead zirconate titanate (PZT) or bismuth strontium tantalate (SBT). The gate electrode 104 is made of a conductor like platinum (Pt). And the source/drain regions 105 and 106 are defined in the substrate 101 and located on right- and left-hand sides of the gate electrode 104. In this device, part of the substrate 101 under the SiO2 film 102 serves as a channel region 107.
In the structure shown in FIG. 6, the ferroelectric film 103 exhibits electric spontaneous polarization of one of the following two types. More specifically, the electric dipole moment in the film 103 is either upward or downward depending on the polarity of a voltage applied between the gate electrode 104 and substrate 101. As used herein, the xe2x80x9cupward electric dipole momentxe2x80x9d refers to the electric moment of electric dipoles showing positive polarity at their upper end, while the xe2x80x9cdownward electric dipole momentxe2x80x9d refers to the electric moment of electric dipoles showing positive polarity at their lower end. The ferroelectric film 103 also shows dielectric hysteresis. That is to say, even after the voltage applied is removed, the polarization of either type remains in the film 103. Thus, the film 103 exhibits one of these two different types of remnant polarization while zero voltage is applied to the gate electrode 104. As a result, the channel region 107 of the FeFET enters one of two different states with mutually different potential depths corresponding to these two different types of remnant polarization. On the other hand, the source-drain resistance of the FeFET changes with the potential depth in the channel region 107. Accordingly, it depends on the type of remnant polarization exhibited by the ferroelectric film 103 whether the source-drain resistance becomes relatively high or relatively low. And one of these two different states, corresponding to the high and low source-drain resistance values, respectively, is retained (or stored) so long as the ferroelectric film 103 keeps its remnant polarization. This is why a nonvolatile memory device is realized by a FeFET like this.
In a nonvolatile memory device using the known FeFET, one state assumed by the ferroelectric film 103 with the down remnant polarization is normally associated with data xe2x80x9c1xe2x80x9d. The other state assumed by the ferroelectric film 103 with the up remnant polarization is normally associated with data xe2x80x9c0xe2x80x9d. To create the down remnant polarization in the ferroelectric film 103, a positive voltage may be applied to the gate electrode 104 with the backside of the substrate 101 grounded, and then the voltage applied to the electrode 104 may be reset to the ground level, for example. The up remnant polarization can be created in the ferroelectric film 103 in a similar manner. Specifically, first, a negative voltage may be applied to the gate electrode 104 with the backside of the substrate 101 grounded, and then the voltage applied to the electrode 104 may be reset to the ground level, for example.
However, no structure proposed so far is highly qualified to operate a FeFET like this fully in an integrated circuit. Accordingly, it is still difficult to sufficiently increase the number of device integrated in, or significantly reduce the overall cost of, a semiconductor integrated circuit including an array of memory cells utilizing the FeFET, a driver circuit thereof, and a logic circuit like a processor.
It is therefore an object of the present invention to make full use of a ferroelectric FET as a memory cell in an integrated circuit by providing a hybrid semiconductor device where a memory and a transistor for controlling the memory are integrated on the same chip.
An inventive semiconductor device includes: a semiconductor substrate; an MISFET, which is provided on the semiconductor substrate and includes a gate insulating film, a gate electrode and source/drain regions; and a ferroelectric FET, which is provided on the semiconductor substrate and includes a ferroelectric film, a control gate electrode provided on the ferroelectric film and source/drain regions.
In this structure, ferroelectric FET and MISFET are provided on the same semiconductor substrate. Accordingly, the ferroelectric FET can be used as a memory cell while the MISFET can be used as a transistor for driving the memory cell. In other words, it is possible to provide a hybrid semiconductor device where a memory cell and a transistor for controlling the memory cell are integrated on the same chip.
In one embodiment of the present invention, the ferroelectric FET preferably further includes: a gate insulating film provided on a part of the substrate, which part is located between the source/drain regions of the ferroelectric FET; a gate electrode provided on the gate insulating film of the ferroelectric FET; an interlevel dielectric film covering at least the gate electrode of the ferroelectric FET; an intermediate electrode provided on the interlevel dielectric film; and a contact member connecting the intermediate electrode and the gate electrode of the ferroelectric FET together. And the ferroelectric film is preferably provided on the intermediate electrode. In such an embodiment, the interlevel dielectric film exists between the ferroelectric film and the semiconductor substrate. Accordingly, the constituent elements of the ferroelectric film will not diffuse and reach the substrate. As a result, the ferroelectric FET will not operate erroneously.
In another embodiment, the gate electrode of the ferroelectric FET and the gate electrode of the MISFET may be formed out of the same conductor film. In such an embodiment, the fabrication cost can be reduced.
In still another embodiment, the inventive device preferably further includes a first interconnect connected to the intermediate electrode; and a second interconnect connected to the control gate electrode. And polarization may be created in the ferroelectric film with a voltage applied between the first and second interconnects. In such an embodiment, the absolute value of the voltage applied when downward polarization should be created in the ferroelectric film can be arbitrarily made different from that of the voltage applied when upward polarization should be created in the ferroelectric film. As a result, data can be written on the ferroelectric film so that no read error will occur due to the disturb phenomenon that decreases the remnant polarization of the ferroelectric film little by little.
In yet still another embodiment, the inventive device preferably further includes: a memory circuit block, in which the ferroelectric FETs are arranged; and a control circuit block, in which the MISFETs are arranged, for controlling the memory circuit block.
An inventive method for fabricating a semiconductor device includes the steps of: a) forming a gate insulating film and a gate electrode for each of first- and second-channel-type MISFETs and a ferroelectric FET over a semiconductor substrate; b) implanting ions of a dopant for forming source/drain regions from over the gate electrode of the ferroelectric FET and the gate electrode of one of the first- and second-channel-type MISFETs; c) implanting ions of another dopant for forming source/drain regions from over the gate electrode of the other MISFET; d) forming an interlevel dielectric film covering the gate electrodes of the MISFETs and the ferroelectric FET, forming a contact hole, which passes through the interlevel dielectric film to reach the gate electrode of the ferroelectric FET, and then filling the contact hole with a conductor material to form a contact member; and e) forming an intermediate electrode, a ferroelectric film and a control gate electrode over the interlevel dielectric film so that the intermediate electrode is connected to the contact member and that the ferroelectric film is in contact with an upper surface of the intermediate electrode and that the control gate electrode faces the intermediate electrode with the ferroelectric film interposed therebetween.
In one embodiment of the present invention, the inventive method preferably further includes the steps of: f) forming an upper-level dielectric film on the interlevel dielectric film after the step e) has been performed; g) forming two contact holes, which pass through the upper-level dielectric film to reach the intermediate and control gate electrodes of the ferroelectric FET, respectively, and then filling the contact holes with a conductor material to form first and second contact members, which make electrical contact with the intermediate and control gate electrodes, respectively; and h) forming first and second interconnects, which are connected to the first and second contact members, respectively, on the upper-level dielectric film.